During manufacture of integrated circuits, a planarization process is often utilized to flatten the surface of a semiconductor wafer. There are many methods of performing the planarization process. When global planarization is required, chemical mechanical polishing, as an alternative to other etchback techniques, is utilized to polish the top layer of the semiconductor wafer.
As shown in FIG. 1A, the conventional chemical mechanical polish (CMP) apparatus includes a polishing pad 10 and a polishing head 12. The polishing pad 10 is configured to have a round shape. A slurry typically consisting of colloidal silica, dispersed aluminum and KOH or NH.sub.4 OH is applied to the top surface of the polishing pad 10. The polishing pad 10 rotates in a counterclockwise direction, while the polishing head 12 rotates in a clockwise direction. As shown in FIG. 1B, a semiconductor wafer 11 is positioned between the polishing pad 10 and the polishing head 12. The diameter of the polishing pad 10 is greater than the diameter of the semiconductor wafer 11. The semiconductor wafer 11 is secured on a top surface of the polishing pad 10 by the polishing head 12. In particular, the polishing head 12 uses a vacuum chuck set 15 to secure the semiconductor wafer 11. In this way, the semiconductor wafer 11 is held by the polishing head 12, while the front surface of the semiconductor wafer 11 is pressed against the top surface of the polishing pad 10. The semiconductor wafer 11 spins with the polishing head 12 in a clockwise direction.
During polishing, the polishing head 12 rotates with a predetermined speed and presses the semiconductor wafer 11 against the polishing pad 10 so that the semiconductor wafer 11 is polished against the polishing pad 10. The polishing pad 10 is fixed on the surface of a rotatable table 14, which spins in a counterclockwise direction, driving the polishing pad 10 in the same direction. In this manner, the semiconductor wafer 11 is polished at a particular polish rate.
FIG. 1C is a simplified graph depicting the polish rate of the semiconductor wafer 11 as a function of the diameter of the semiconductor wafer 11. It will be appreciated that the polish rate has larger values near the rim of the semiconductor wafer 11 compared to the center of the semiconductor wafer 11. The nonuniformity in the polish rate of the semiconductor wafer 11 increases with an increase in the size of the semiconductor wafer 11. For example, the nonuniformity in the polish rate for 12-inch semiconductor wafers is more dramatic than for 8-inch semiconductor wafers.
One primary disadvantage of the conventional chemical mechanical polish involves the nonuniformity of the polish rate. The nonuniformity is caused by a variety of factors. First, the rotating orientation of the semiconductor wafer 11 relative to the polishing pad 10 causes nonuniformity. Also, the top surface of the polishing pad 10 is typically not planar. As a result, its nonplanar orientation is undesirably transferred to the semiconductor wafer 11 during polishing. Furthermore, the pressure applied by the polishing head 10 to the semiconductor wafer 11 may be nonuniform, causing the polish rate on the surface of the semiconductor wafer 11 to be nonuniform.